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SV51004
2013.05.06
Document Revision History
3-27
Signal Name
ACLR0
ACLR1
Function
Variable precision DSP-block-wide asynchronous clear signals
Total Count per DSP Block
Count
2
14
Document Revision History
Date
May 2013
Version
2013.05.06
Changes
? Added link to the known document issues in the Knowledge Base.
? Moved all links to the Related Information section of respective topics
for easy reference.
December 2012
2012.12.28
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Added "Design Considerations"
Updated Figure 3-1 changed Mult_L and Mult_H to Multiplier
Updated Figure 3-6 changed Mult_L to Multiplier
Updated Figure 3-7 changed Mult_L and Mult_H to Multiplier
Updated Figure 3-8 changed Mult_L and Mult_H to Multiplier
Updated Figure 3-10 changed Mult_L and Mult_H to Multiplier
Updated Figure 3-11 changed Mult_L and Mult_H to Multiplier
Updated Figure 3-13 changed Mult_L and Mult_H to Multiplier
Updated Figure 3-17 changed Mult_L and Mult_H to Multiplier
Updated Figure 3-19 changed 54 to 55
Updated Figure 3-20 changed 19 to 18 and deleted Chainout [38..0]
Updated Figure 3-23 changed Mult_L to Multiplier
Updated Figure 3-24 changed Mult_L and Mult_H to Multiplier and
added 44
? Updated Figure 3-25 added 64
? Reorganized content and updated template.
June 2012
1.4
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Added Figure 3 – 2.
Updated Figure 3 – 7, Figure 3 – 16, and Figure 3 – 18.
Updated Table 3 – 1.
Updated “ Chainout Adder and Accumulator ” and “ 18 x 25 Complex
Multiplier ” sections.
November 2011
1.3
? Added Figure 3 – 21.
? Updated Figure 3 – 1, Figure 3 – 2, Figure 3 – 11, Figure 3 – 12, Figure 3 – 14,
Figure 3 – 16, Figure 3 – 17, Figure 3 – 18, Figure 3 – 19, Figure 3 – 20, and
Figure 3 – 21.
? Updated Table 3 – 1 and Table 3 – 5.
? Updated “ Pre-Adder and Coefficient Select ” , “ Systolic Register ” , “ Systolic
FIR Mode ” , and “ Software Support ” sections.
Variable Precision DSP Blocks in Stratix V Devices
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